Materials-Enabled 3D Scaling: The Path to More Energy-Efficient AI

AI's growth is now bottlenecked by energy, measured in tokens per second per watt. Mukund Srinivasan, Group Vice President and General Manager of the Technology Solutions Group at Applied Materials, says the chip and packaging layer delivers the biggest gains on that metric.

At the Six Five Summit: AI Unleashed 2026, Srinivasan spoke with Patrick Moorhead for a Semiconductors Spotlight interview on how 3D scaling across logic, memory, and packaging is replacing the transistor shrink that once defined chip roadmaps.

In logic, the transition from FinFET to gate-all-around transistors lowers operating voltage and reduces power even as transistor counts rise. In memory, high bandwidth memory and other stacked configurations increase capacity while shortening the distance data must travel. Advanced packaging brings compute and memory physically closer, reducing both latency and energy consumption.

The shift from tungsten to molybdenum contacts offers a clear example of the materials engineering behind these advances. Tungsten resistance rises sharply at two-nanometer dimensions, leading Applied Materials to develop Spectral Moly ALD, which reduces contact resistance by roughly 15 percent. Hybrid bonding, the company’s Kinects alignment tool, and e-beam metrology capable of detecting defects at the angstrom level support the same broader effort.

AI demand is also growing faster than new fabs can be built. Applied Materials is responding by helping manufacturers produce more good chips from existing fab space through greater tool uptime and tighter process control. Its Epic collaboration center, scheduled to open later this year, is designed to bring materials engineers, system architects, and chip designers together earlier in the development process.

Key Insights:

🔹 Energy efficiency is becoming a defining constraint on AI growth. Applied Materials measures progress in tokens per second per watt, and Srinivasan says the chip and packaging layer offers the greatest opportunity for improvement.

🔹 3D scaling is replacing traditional transistor shrink across the semiconductor stack. Gate-all-around transistors lower voltage in logic, stacked memory such as HBM expands capacity, and advanced packaging moves compute and memory closer together.

🔹 New materials are needed as existing ones reach their physical limits. Applied Materials developed Spectral Moly ALD to replace tungsten contacts at two-nanometer dimensions, reducing resistance by roughly 15 percent.

🔹 Existing fabs must produce more while new capacity comes online. With AI demand outpacing fab construction, Applied Materials is focused on increasing tool uptime, improving process control, and producing more good chips from the same footprint.

🔹 Epic is designed to accelerate the path from materials innovation to scaled production. The collaboration center will connect materials engineers with system architects and chip designers earlier, shortening the journey from laboratory breakthrough to high-volume manufacturing.

Srinivasan ultimately frames semiconductor progress as an integration challenge. A change made 30 or 40 process steps earlier can affect results much later in production. Applied Materials is betting that its portfolio across materials, equipment, and metrology will allow it to optimize the entire manufacturing chain as one interconnected system.

Watch the full session at sixfivemedia.com/summit, and explore the rest of our Six Five Summit: AI Unleashed 2026 Semiconductors Spotlight coverage.

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Mukund Srinivasan:

3D scaling is here. It's happening across the entire semiconductor domain. It's happening in the XPU, which is the logic compute. It is happening in memory. It is happening in packaging, which puts the logic and the memory together.

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Patrick Moorhead: 

Hey everybody, welcome to Six Five Summit 2026. The theme of this year is AI Unleashed. But before we get to that unleashed part, there's a lot of infrastructure that needs to happen. And whether it's chips, whether it's servers, storage, networking, and oh, by the way, the equipment that makes it all happen. We're in the Semiconductor Spotlight. And in this session, we're going to be exploring how the semiconductor industry is responding to this enormous compute and energy demands that's being driven by AI. I'm joined today by Mukund, who's Group Vice President, General Manager of the Technology Solutions Group at Applied Materials. Mukund, welcome to The Six Five.

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Mukund Srinivasan: 

Hi, Patrick. Great to be here.

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Patrick Moorhead: 

Yeah, it is amazing. I think seven or eight years ago, I met with somebody in the press and they said, hey, this is a tier one business person. And they said, hey, we don't think we're going to cover semiconductors anymore because we don't think people are are interested in it, but is truly amazing, the fascination that has hit. And I'm glad to be part of it. So we had your CEO, Gary, on earlier. And the way he described the landscape was a global race for AI leadership, which is not only driving the unprecedented demand for compute, but also driving a tremendous amount of power. From the semiconductor perspective, what does the industry need to do to make the biggest gains to keep AI scaling sustainably and reasonably?

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Mukund Srinivasan: 

Yeah, thanks a lot, Patrick. I think it's an unprecedented time in this industry. I would say AI, if I look at the landscape today, there are two big challenges that need to be solved concurrently. One is the technology aspect of it, and the other one is the capacity aspect of it. If we look at the technology challenge, it's very clear that, you know, more data, more compute, and the communication between the two consumes more energy. So energy efficiency is a first order objective. And typically, it's measured in, you know, tokens per second per watt. And When we look at energy efficiency, there is no question energy efficiency has to be optimized across the stack. But the different parts of the stack have different impact. And the semiconductor chip and packaging layer is where the maximum and the most critical gains are to be had. So that, I would say, is the technology aspect of it. On capacity, the industry must find more effective ways of meeting AI demand by getting more good chips out per month. Of course, there's a lot of conversation about bringing more capacity, more new fabs online. There's no question that has to happen. But if we look at what is going on, a lot of our customers who operate these fabs are looking at how to optimize the existing space. So there is how do you optimize existing space? How do you bring more capacity online and solve all the technology challenges? I think those are, I would say, the three biggest areas of focus for the industry and of course, for applied materials.

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Patrick Moorhead: 

Yeah, the variability and even designs that your customers have to deal with are amazing. And just in data center compute right now, there's five different types of architectures just to do the compute. multiple architectures to drive networking, different architectures for memory. And with growth, a lot of times comes heterogeneity and fragmentation, which for your customers and even for you makes a more complex world. But that's what we have to do to hit that performance per watt number. Scaling has, you know, it's funny, back to my days as a chip maker. I worked for a chip maker for 11 years and then 10 years before that I was, I was an OEM buying chips from the chip makers and it was always about the shrink. Right, like, the transistor size, right? And almost nothing else matter. And quite frankly, even the packaging was given to the B-team. But 2D scaling has reached its physical and economic limits. How is the industry, your customers and you, really reinventing their roadmaps to deliver the most energy efficient compute AI for their demands?

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Mukund Srinivasan: 

Yeah. So Patrick, if, if we look at what is the biggest objective, the biggest objective is, you know, how do you reduce the total energy and at while, you know, increasing the performance. So, as you rightly mentioned, 3D scaling is here. It's happening across the entire semiconductor domain. It's happening in the XPU, which is the logic compute. It is happening in memory. And of course, it is happening in packaging, which puts the logic and the memory together. So let's go through it one by one. If I look at logic, more compute requires more transistor, you know, much, much better wiring. So the industry is transitioning from what they call the FinFET architecture, which is really where most of the GPU and CPU manufacturing is today. It will transition to the gate all around architecture. And one of the biggest advantages of gate all around architecture is it operates at lower voltage. Lower voltage equal to lower energy consumption because the energy consumption goes as the square of the voltage. So even though you are increasing the number of transistors to get more compute, you're reducing the compute per watt by lowering the voltage. In memory, of course, there's a lot of discussion around high bandwidth memory. High bandwidth memory is essentially 3D scaling of DRAM, right? But it's not just high bandwidth memory is one embodiment of 3D memory. There is plenty of other embodiments where they are stacking logic onto SRAM. They are now talking about DRAM stacked on top of logic. So again, there you want to increase the bandwidth between the memory and compute, but at the same time, do it in the most energy efficient way. So then the third aspect of it is advanced packaging, as you said, The world of packaging is completely changed upside down. It is the critical enabler for bringing both compute and memory closer together. And the closer the compute and memory are, the faster compute gets the data. and the lower energy consumption in moving the data between memory and compute. So it all plays a big role in optimizing performance per unit watt. So of course, Applied Materials is really able to get a good vantage point across all these inflections. And we are looking forward to solving all these challenges along with the rest of the industry in the years to come.

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Patrick Moorhead: 

Yeah, it's funny. I was joking with Gary in the green room before our video. I'm like, Gary, like, you know, everything about every chip and almost every package that's going to happen for the next five years. And he just looked at me and he just smiled. But somebody has to be ahead of this. And as you know, the chip guys, they deserve a lot of credit. The foundries deserve a lot of credit, but the WFE companies, AI doesn't happen with companies like Applied Materials. Hey, I wanna move on to this variability, right? Going 2D to 3D, the heterogeneity of compute, and there used to be a day when there was maybe only three different kinds of memory, okay? And now we have, I would say, 12 different types of memory in market. And at the Memory Show a few weeks back, discussions of all these new architectures. And we've got companies coming out with HBC, which is stacking DRAM on top of Logic. If the Foundry business is a scaling business, which it still has to be given the hundreds and billions of dollars in CapEx, What are some of the new innovations to make all this 3D scaling practical to your customers?

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Mukund Srinivasan: 

Yeah, that's a great question, Patrick. And this is something that we here at Applied focus on day in and day out. I would say the foundational building blocks to enable 3D scaling, I think, fall into four categories. One is innovation in materials. And typically that innovation centers around lowering the resistance, lowering the capacitance, because in these advanced chips, there is so much wiring and the data moves through, you know, thousands of kilometers of wires, you need to have low resistance and you need to have low capacitance. The other area of innovation is on selective processing. What I mean by selective processing is the ability to deposit and etch materials in certain parts of the structure and not touch it in other parts of the structure. And these two parts are located within a few angstroms, right? So really unique and breakthrough innovation is needed to enable that. Then the third aspect, you talked about process control. As we go to finer dimensions and go to three dimensions, tighter process control is another big area. The fourth aspect of the innovation centers around how do you put it all together? How do you integrate it to optimize the performance? So those are, you know, I would say the four challenges. So if I can give a few examples for this. So we talked about loading resistance and capacitance with new materials. One example of it would be in contacts. If you look at the industry, you know, these contacts have historically been made with tungsten. Tungsten is a great material that served the industry well for decades. However, as these dimensions shrink, especially at two nanometer, the tungsten resistance rises sharply. And that's related to scattering effects at these small dimensions. And then when the resistance goes up, it becomes a huge performance bottleneck. So the industry was looking to transition to a new material, and that material is moly. So we've been hard at work here at Applied Materials in the past few years. trying to bring this MOLLE contact to the market. And it isn't as simple as just replacing a material. It is co-optimization between the material properties, the equipment that deposits that material in these fine geometries. So we announced a new product called Spectral MOLLE ALD that allows us to deposit moly effectively replaced tungsten. And we are seeing great results. You know, the resistance of the moly is about 15% lower than tungsten. So that's one example of materials innovation. We talked about selective processing and, you know, applied as pioneered and leads in selective processing. And here are some of the innovations that are required is how do you combine deposition, chemistry, innovation, and etching all in the same chamber, typically the deposition equipment, and the etching equipment were separated. But for selective deposition, because it's a very cyclic process, you got to combine it all in the same chamber. So that's another area where Applied is pioneering the use of selective deposition. Also, lots of treatments and material modifications have become important. As we go to 3D scaling, the interfaces become as thick as the bulk itself. It's hard to distinguish the bulk material from the interface material. So how you handle these interface materials is very important. And we have a number of different treatment technologies. Viva is one of the examples of a treatment technology that can smooth the silicon at an angstrom level. It's hard to imagine that smoothing the silicon by one angstrom or two angstroms can make a difference, but it has an enormous impact on the device. And then on the packaging side, there is this new technology called hybrid bonding that essentially replaces the use of bumps in certain parts of the packaging architecture. And by bringing the chips closer together, it not only enables boosting wiring density and bandwidth, But the closer you get, the energy efficiency also improves. Now, to enable hybrid bonding, a number of different processes have to come together. One example is CMP, because you need to get the chip surface perfectly planar for successful bonding. And then the other product which we introduced last year into the market is called Kinects that essentially combines a number of different technologies to precisely align and bond these chips together at scale. The last one we talked about the challenges process control. Angstrom level control is required. I talked about the interface and the bulk kind of merging, but you know, you can only control what you can measure. So the ability to measure and capture defects at scale within the dye and across the wafer at angstrom level, is crucial. So today, if you look at process control technologies, the optical inspection, optical metrology has been the baseline. But as we move forward, optical really struggles to capture tiny defects at scale, right? So again, one of the technologies that we've worked on is this E-beam technology that can image 3D features at far better resolution versus optical. So in, in essence, by co-optimizing the process along with the metrology accelerates the learning rate and improves yield. So that's really key to process control is how do you find these defects and how do you fix those defects? And here at Applied, we are able to you know, co-optimize both because we develop the metrology and inspection tools with E-beam capabilities. And of course the process technologies for deposition, etch and treatments. So I would say that the last challenge that we should not ignore is the integration complexity, right? 3D manufacturing is very new to the industry. You know, the industry has been on a 2D scaling roadmap for decades now. So as you go into 3D, the complexity increases, but we are also finding the step-to-step dependencies grow. Sometimes what happens, you think you've done a good job in a particular step. but another step that occurs 30 or 40 steps later affects what you did in this particular step. So having a more holistic understanding of the integration flow and optimizing it for both downstream and upstream effects is really critical. And here it applied because we have this broad portfolio, it lets us optimize these multiple steps. And we have, you know, talked about a number of these integrated products like Kinects, the Endura, or copper deposition and so on.

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Patrick Moorhead: 

Yeah. So, Mukund, as you went through the four innovation areas, and I get to this certain point of conversations like this, that how do we get any of this stuff to actually work in a chip? The one area we haven't done a double-click into is another major challenge, and that's capacity. And you had talked about increasing capacity and throughput inside of a current fab that's already there. There's also the standing up new ones and new ways to do that. How are you helping the capacity challenge?

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Mukund Srinivasan: 

Yeah, that's a very important question. If I look at the winners today, they are defined not just by technology innovation, but also the ability to ramp, yield, and scale. It's very clear that the AI demand is growing faster than the manufacturing capacity that is coming online. And that's partly because new fabs take years to build and ramp. It takes a long time to get the supply chain in place to ramp at this unprecedented rate. So when I look at this capacity challenge, obviously how fast you can bring new fabs online is one of the important factors, but more and more our customers are also looking at what are the productivity and yield gains that can happen right now to unlock more output from existing fabs. And, you know, at the beginning of this conversation, I talked about good chips out per month. That is the key. And customers are looking to do that in multiple ways. And so unlocking the potential of existing fabs is a fast way to get good chips out per month. So here at Applied, we are looking at new tool designs that optimize fab utilization. There's nothing that is more precious than fab space right now. So how do we get our tools to operate uh, better inside the existing fabs with greater uptime, as well as how do you operate, uh, with better process control? Because today, if you look at the process windows, they're getting narrower and narrower. So having better process control to maximize yield is a crucial aspect. So both productivity and yield Plus, bringing new fabs online fast is, I believe, the best way to solve these capacity bottlenecks.

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Patrick Moorhead: 

Yeah, so you're tackling a lot there. By the way, great conversation so far. We've got time for one more question. So I told you I visited your Epic facility that's under construction. And the whole thesis there is we're going to co-innovate, we're going to shrink time to market, and do a lot of things at the same time that may or may not have been done in a serial fashion. And I'm sure Epic's just one example, but how does all this earlier collaboration change the way the industry identifies and solves the bottlenecks that could actually limit AI scaling?

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Mukund Srinivasan: 

Yeah, well, first, I think we're all here at Applied very excited about Epic. We believe that it is going to be a very key strategy to unlocking this innovation that is required to keep the AI roadmap on track. So our strategy is really around inflection-focused innovation, where we talked a lot about 3D scaling, for logic, memory, and packaging. And that's the core to what Epic will do in the coming years. We've been in constant dialogue with leading foundries, all the fabs who are our customers, but we are also working more closely with our customers' customers, the system architecture, the architects, the chip designers. And that is a big change in the industry because That is a growing realization that the ecosystem needs to come together to solve these future problems. So while applied previously was about connecting devices to materials and solving the challenges in that loop, that still remains very critical. But now as we look at the AI challenges, connecting system to materials is key. And that's where Epic comes in by bringing the ecosystem of the hyperscalers, the fabulous companies, the customers who are doing leading edge R&D in making chips, both logic and memory and packaging. I think bringing that ecosystem together in Epic and driving high-velocity co-innovation, that's really what Epic is all about. And hopefully by doing that, we want to be able to help shape the roadmap, develop solutions along with our partners and our customers. We're very excited again as the Epic Center is opening later this year, and we think it's going to play a big role in this inflection focused innovation. And I think the key for us is how can we accelerate the roadmap. right? So it's, you know, the C for in EPIC stands for commercialization. So it's not just about innovation. It's about bringing these breakthrough technologies into high volume manufacturing so the benefits can be realized faster.

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Patrick Moorhead: 

Great conversation. And I will reiterate that every time I have a conversation like that, I can't even believe that at the end of the day, we can create as an industry, the semiconductors that we do. And like I always like to say, and I think your PR people like this, I mean, AI doesn't happen without applied materials. I think more people need to fully understand that and you're making the investments. I really didn't know what I was walking into Epic. I was thinking, hey, it's this small little building and people are going to have fun and it's going to be a demo center. I mean, it's like a whole foundry, right? I couldn't believe it, right? But you kind of had to go there and the thousands of workers that that are in a tent eating lunch in their suits, the clean room build out is truly impressive. So, Mukund, thank you so much for this conversation. Patrick, it was great talking to you. Thank you very much. Thanks. And to our viewers, don't forget to hit that subscribe button. Follow us on all socials. Check out all of our Semiconductor Summit coverage at sixfivemedia.com. Stick around for more great semiconductor content coming up next.

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