What Comes After the Breakthroughs That Saved Transistor Scaling? An Intel Perspective

Chris Auth doesn't think scaling means what it used to. The Intel Foundry Vice President and General Manager of Manufacturing Development and Customer Engineering says the industry has moved from optimizing cost per transistor to optimizing value per transistor: performance, power efficiency, heat, and how a chip fits into a larger system, not just how small the process node gets.

"...it's more of the value per transistor that starts to become important." — Chris Auth, Vice President and General Manager, Manufacturing Development and Customer Engineering, Intel Foundry

At the Six Five Summit: AI Unleashed 2026, Ryan Shrout and Anshel Sag asked Auth what's driving that change. He points to two architecture shifts: Gate-All-Around transistors, which give the gate full control over the channel instead of the partial control FinFETs allowed, and backside power delivery, which moves power interconnects to the back of the chip so they can carry more current without crowding the signal lines on the front. Auth expects that combination, paired with rapid advances in hybrid bonding and 3D packaging, to serve as the foundation for chip architecture well into the next decade.

Key Insights:

🔹 Scaling has shifted from cost per transistor to value per transistor, Auth says, meaning performance, power efficiency, thermals, and system-level fit now matter as much as raw process node size.

🔹 Gate-All-Around transistors give the gate full control over the channel, solving the partial-control limitation that capped how far FinFET transistors could scale.

🔹 Backside power delivery separates power and signal interconnects onto opposite sides of the chip, letting power wires run larger and lower-resistance without crowding signal lines.

🔹 AI's demand for inference is driving what Auth calls a resurgence of the CPU, since inference workloads need an orchestrator to manage memory and compute for each unique query, not just raw GPU throughput.

🔹 Auth expects no single breakthrough over the next five years. Instead: successive generations of Gate-All-Around transistors and backside power, layered with more advanced hybrid bonding and 3D packaging.

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Chris Auth:
That's where backside power comes in, where we took the power wires and we put them on the backside. So now they can be big and fat; they can bring power directly into the transistors, and on your front side you now can have your signal lines which talk to each other. This combination is really going to be the foundation for semiconductors for well into the next decade.

Ryan Shrout: 

Hey everybody, welcome to Six Five Summit AI Unleashed 2026. For this semiconductor spotlight, I'm joined by my colleague Anshul Sag. Anshul, good to see you. 

Anshel Sag: 

Thanks for having me again. 

Ryan Shrout: 

And we're going to be exploring what comes next after the innovations that basically gave us Moore's Law, gave Moore's Law a second life, if you will. We're going to talk to somebody who has a lot of experience there. We're going to talk through how AI is driving demand for additional compute and efficiency and how kind of this next generation of transistor technology really is going to drive an impact. So let's welcome in our guest, Chris Auth, who is the Vice President and General Manager of the Manufacturing Development and Customer Engineering Group at Intel Foundry. Chris, thanks for joining Six Five.

Chris Auth: 

Ryan, thanks for having me. Wonderful to be on your show.

Anshel Sag: 

Chris, your work on strained silicon and high K metal gate fundamentally changed the trajectory of the semiconductor scaling. Looking at where the industry stands today, why does this moment feel like another major architectural turning point rather than simply the next process?

Chris Auth: 

Yeah, that's a good question. It's great to kind of look back at the broader history of transistors and interconnects. If you go back kind of the 80s and 90s, the traditional Moore's law, just scale, baby, scale was kind of the mantra. You get a new lithography and you scale, transistors get faster, interconnects get faster. Everything was great. And then we kind of hit the dot-com boom and into the 2000s and things really changed there, which kind of became this golden age of innovation where you had to do materials and architecture changes, whether it's strained silicon, high K metal gate, FinFET transistors. And what we see now is not only do we have transistor and interconnect innovation with gate all-round transistors, brand new transistor architecture, and then we have backside power, which is a new interconnect scheme. But you're also seeing this explosion of innovation on the packaging side. So HBM, how you get memory, how you, you know, even we're starting to talk about optical interconnects and so forth. You kind of have a few things going on besides just a node transition with data around backside power, but you also have packaging on top of that. And how you optimize that is kind of the brave new world we're starting to go into.

Ryan Shrout: 

It's interesting you mentioned the kind of this, that traditional reliable scaling that you got for years and decades just by kind of shrinking transistors. I lived through a lot of it as an observer. right into the consumer of those products, it was great to see. But, you know, we seem to be hitting a different kind of wall, different kind of threshold with these other AI and high compute workloads that really push against these limits of power and efficiency that you described. How's the industry's definition of scaling itself really changed because of this? And kind of what changes have to take place in the market or in the industry to keep driving those performance improvements?

Chris Auth: 

No, it is scaling used to be really heavily focused on kind of cost per transistor. And there was like every generation you want to hit a certain cost per transistor reduction. And I think what you're seeing now is that there's more to it than that. I would say it's more of the value per transistor that starts to become important. So it's, hey, what is the performance that you get? What is the power efficiency that you have? You know, how do you not produce a lot of heat? So you don't have a lot of thermal issues. And then how do you take it from, is it just one chip that you're making? Is it chiplets that you have for some sort of packaging? type 3D type structure. And so these have kind of changed what the end customer is looking for in a, you know, as you go from technology node to technology node that you need to optimize, not just for a particular chip, but also the overall system that you're trying to create.

Ryan Shrout: 

There's a lot of interesting analogs in my view about that line of thinking and kind of how we've seen the whole compute paradigm shift as well, where we used to think of it purely as straight line, single-threaded compute as the primary driver of performance. And now it's multi-cores, multi-IP, different memory packages that kind of all add up into it in the same way. Is there like a reason for that similarity, do you think?

Chris Auth: Yeah, I think that, you know, AI is definitely driving a big change. You know, if you go back even just as recently as six months, six to nine months ago, it was very heavy on this kind of GPU, just raw compute, run it through. But it's been interesting over the last six, nine months, what we've seen is kind of this shift to where you need this kind of conductor or orchestrator to manage memory as you know, because really AI drives inference and inference is not necessarily just one thing over and over again. It's somebody writing in and doing LLM. Hey, what about this? And so it has to go do a query. And that's going to be unique to whatever the user is looking for. And so it has to use memory, it has to use compute. And you need some orchestrator for that. Luckily, we do have a something that can do that. And that's the CPU. So you've seen this resurgence of the CPU is kind of becoming central to the whole AI explosion that you have.

Anshel Sag: 

You mentioned a little bit about gate all-around transistors and backside power. And you talk about how they kind of represent one of the biggest device architecture changes in decades. And without maybe getting into too much implementation details, what are the problems that these technologies solve that previous transistor designs could no longer address?

Chris Auth: 

Yeah, they're really cool technologies. As kind of a transistor junkie, the gate all-around transistor is kind of your ultimate transistor. If we go to what's been used for like the past decade or so, it's FinFET transistors. And FinFETs were a revolution at the time, going from a planar transistor, which was flat, to now this 3D structure of vertical fins. And the way the transistor works, it's really a switch, and it has a channel where current flows, and there's a control gate. And in a FinFET, the control gate wraps around the top, but it doesn't control the bottom, which is kind of the Achilles heel of it. And that prevents further scaling. The gate all around has a gate which completely surrounds it, so it has total control over the channel. So that enables it to continue to scale. On the interconnect side, backside power, you have really two types of interconnects. You have power interconnects, which bring power from the outside world into the transistor. And they want to be big and fat, low resistivity, bring as much power as you can to the transistor. And then you have signal lines. And those signal lines allow the transistors to talk to each other. And they want to not have any interference from other signal lines. So they want to be far away from everything else, which makes them small with big spaces. And so on the interconnect side, you have these two opposing types of interconnects. And that's where backside power comes in, where we took the power wires and we put them on the backside. So now they can be big and fat. They can bring power directly into the transistors. And on your front side, you now can have your signal lines which talk to each other. This combination is really going to be the foundation for semiconductors for well into the next decade. Even if you talk about some of the future technology structures such as CFET, it's, again, just data around transistors. They're stacked one on top of each other. And they will have backside power as part of it. So it's really kind of a the beginning of what will be a very long decade or multi-decade type architecture.

Ryan Shrout:

I want to ask you about that decade, because as the silicon manufacturing innovation moves into power delivery and packaging and these system level integrations, are you seeing customers, whether it be Intel or other external Intel foundry customers, think differently about how they design their semiconductor platforms for AI and or for anything else high performance?

Chris Auth: 

Yeah, it really is changing because a lot of what we had before was when you looked into packaging or chiplets, you would still do a chip level optimization and you say, OK, this is this is the chip that I want. And then. It was kind of an afterthought to put it into a package or a high-level system. And what we're seeing is really kind of this change to where now the designers are coming to me and saying, hey, this is what I want to do from a system level. What does that mean for each of the chips that we need to optimize? What technology node should they go on? How should we optimize them for power versus thermals versus a variety of different optimizations that you may want to do. So there's kind of this more system level thought process that's going into AI because now you do have these very complex 3D structures with memory and compute and IO all on these 3D structures.

Anshel Sag: 

Chris, looking ahead, if we revisit this conversation five years from now, what developments do you think we'll point to as the breakthroughs that unlock the next era of semiconductor performance? And what should the industry be investing in today to make that future possible?

Chris Auth: 

Yeah, if I look at, you know, five years ahead or so, I'm not sure I would say there's going to be one breakthrough that's really going to going to change things. I think you're going to see a lot of innovation that's going to occur on the transistor side. You're going to see a second, maybe a third generation of gate around transistors, a second or third generation of backside power. And then on top of that, you've got innovation on the packaging side. So hybrid bonding is kind of the rage right now. But I think we're at the infancy of where hybrid bonding can go, because we're kind of just doing very simple, straight two wafers or two chips. And, you know, it's very wide pitches, I think, as we see the pitches scaling, and we start to do more exotic designs, we'll have multiple chips of, say, memory, a few compute IO, and then you'll sandwich that on top of some other compute. You'll see a pretty dramatic look at packaging. I mean, packaging today versus what it was a decade ago, it would kind of blow your mind as far as how much things have changed, much like the transistors and interconnects. If I showed you get around backside power back in the 90s, it would blow your mind. You'd be like, oh, my gosh, this is this is totally bonkers that we have, you know, a transistor that's sandwiched between interconnects. And you can imagine that now that you have demonstrated you can do that, you could actually sandwich several transistors and several interconnect stacks in there. So I think those are where you're going to start to see the breakthroughs is this layering of transistors, interconnects on top of packaging different types of IP.

Ryan Shrout: 

Chris, I want to thank you for joining us here on the Semiconductor Spotlight. I love talking about transistors and technology and process nodes. It's something that has always been of significant interest to me. It still seems like magic. And so I am in awe of the type of work that you and the team really put in there.

Chris Auth: 

Well, thank you, Ryan, for having me. It's a topic I love to talk about.

Ryan Shrout: 

Alright, and to our viewers, don't forget to hit subscribe, follow us on social media, and check out all of our Six Five Summit content at sixfivemedia.com slash summit. See you next time.